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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
interrupt-response timing
The following table defines the timing parameters for the INT signals.
timing parameters for INT3−INT0 [Q = t
] (see Figure 21)
c(H)
320C30-40
320C30-50
NO.
UNIT
MIN
13
MAX
MIN
10
MAX
61
62
t
t
Setup time, INT3−INT0 before H1 low
ns
ns
su(INT)
Pulse duration, INT3−INT0, to assure only one interrupt seen
Q
< 2Q*
Q
< 2Q*
w(INT)
* This parameter is not production tested.
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
SMJ320C30 interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
D
D
A minimum of one H1 falling edge
No more than two H1 falling edges
The SMJ320C30 can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 21 occurs; otherwise, an additional delay
of one clock cycle is possible.
Reset or
Fetch First
Instruction of
Service Routine
Interrupt
Vector
Read
H3
H1
61
INT3−INT0
Pins
62
First
Instruction
Address
INT3−INT0
Flag
Vector Address
Addr
Data
Figure 21. Timing for INT3−INT0 Response [Q=t
]
c(H)
30
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