RM46L450
RM46L850
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SPNS184 –SEPTEMBER 2012
4.14.2.4 Write Timing (Synchronous RAM)
1
BASIC SDRAM
WRITE OPERATION
2
2
EMIF_CLK
EMIF_CS[0]
3
5
7
7
9
4
6
EMIF_DQM[1:0]
EMIF_BA[1:0]
8
8
EMIF_ADDR[12:0]
10
EMIF_DATA[15:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
11
12
13
15
16
Figure 4-17. Basic SDRAM Write Operation
4.14.2.5 EMIF Asynchronous Memory Timing
Table 4-28. EMIF Asynchronous Memory Timing Requirements
NO.
Value
NOM
Unit
MIN
MAX
Reads and Writes
2
tw(EM_WAIT)
Pulse duration, EMIFnWAIT
2E
ns
assertion and deassertion
Reads
12
13
14
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
tsu(EMOEL-EMWAIT)
Setup time, EMIFDATA[15:0]
valid before EMIFnOE high
11
0.5
ns
ns
ns
Hold time, EMIFDATA[15:0]
valid after EMIFnOE high
Setup Time, EMIFnWAIT
asserted before end of Strobe
Phase(1)
4E+3
Writes
28
tsu(EMWEL-EMWAIT)
Setup Time, EMIFnWAIT
asserted before end of Strobe
Phase(1)
4E+3
ns
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure Figure 4-13 and Figure Figure 4-15 describe EMIF transactions that include extended wait states inserted during the
STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start
of where the HOLD phase would begin if there were no extended wait cycles.
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