RM46L450
RM46L850
www.ti.com
NO
SPNS184 –SEPTEMBER 2012
Table 4-29. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
Parameter
Value
NOM
0
Unit
MIN
MAX
Output hold time, EMIFnWE
high to EMIFCS[4:2] high (SS =
1)
-3
+3
ns
18
19
20
21
22
tsu(EMDQMV-EMWEL)
Output setup time, EMIFBA[1:0]
valid to EMIFnWE low
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
ns
ns
ns
ns
ns
th(EMWEH-EMDQMIV)
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
Output hold time, EMIFnWE
high to EMIFBA[1:0] invalid
Output setup time, EMIFBA[1:0]
valid to EMIFnWE low
Output hold time, EMIFnWE
high to EMIFBA[1:0] invalid
Output setup time,
EMIFADDR[12:0] valid to
EMIFnWE low
23
24
th(EMWEH-EMAIV)
tw(EMWEL)
Output hold time, EMIFnWE
high to EMIFADDR[12:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
ns
ns
ns
ns
EMIFnWE active low width (EW
= 0)
(WST)*E-3
(WST)*E
(WST)*E+3
EMIFnWE active low width (EW
= 1)
(WST+(EWC*1 (WST+(EWC*1 (WST+(EWC*1
6)) *E-3
6))*E
6)) *E+3
25
26
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
Delay time from EMIFnWAIT
deasserted to EMIFnWE high
3E-3
4E
4E+3
Output setup time,
EMIFDATA[15:0] valid to
EMIFnWE low
(WS)*E-3
(WH)*E-3
(WS)*E
(WH)*E
(WS)*E+3
(WH)*E+3
27
th(EMWEH-EMDIV)
Output hold time, EMIFnWE
ns
high to EMIFDATA[15:0] invalid
Table 4-30. EMIF Synchronous Memory Timing Requirements
NO.
Parameter
tsu(EMIFDV-EM_CLKH)
MIN
MAX
Unit
19
Input setup time, read data valid on
EMIFDATA[15:0] before EMIF_CLK
rising
1
ns
20
th(CLKH-DIV)
Input hold time, read data valid on
EMIFDATA[15:0] after EMIF_CLK
rising
1.5
ns
Table 4-31. EMIF Synchronous Memory Switching Characteristics
NO.
1
Parameter
tc(CLK)
MIN
10
3
MAX
Unit
ns
Cycle time, EMIF clock EMIF_CLK
2
tw(CLK)
Pulse width, EMIF clock EMIF_CLK
high or low
ns
3
4
5
6
7
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
Delay time, EMIF_CLK rising to
EMIFnCS[0] valid
7
7
7
ns
ns
ns
ns
ns
Output hold time, EMIF_CLK rising to
EMIFnCS[0] invalid
1
1
Delay time, EMIF_CLK rising to
EMIFnDQM[1:0] valid
Output hold time, EMIF_CLK rising to
EMIFnDQM[1:0] invalid
Delay time, EMIF_CLK rising to
EMIFADDR[12:0] and EMIFBA[1:0]
valid
Copyright © 2012, Texas Instruments Incorporated
System Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: RM46L450 RM46L850
93
TI [ TEXAS INSTRUMENTS ]
