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RM46L450PGET 参数 Datasheet PDF下载

RM46L450PGET图片预览
型号: RM46L450PGET
PDF下载: 下载PDF文件 查看货源
内容描述: RM46Lx50 16位/ 32位RISC闪存微控制器 [RM46Lx50 16/32-Bit RISC Flash Microcontroller]
分类和应用: 闪存微控制器
文件页数/大小: 172 页 / 2534 K
品牌: TI [ TEXAS INSTRUMENTS ]
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RM46L450  
RM46L850  
www.ti.com  
SPNS184 SEPTEMBER 2012  
4.13.2 On-Chip SRAM Auto Initialization  
This microcontroller allows some of the on-chip memories to be initialized via the Memory Hardware  
Initialization mechanism in the System module. This hardware mechanism allows an application to  
program the memory arrays with error detection capability to a known state based on their error detection  
scheme (odd/even parity or ECC).  
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects  
the memories that are to be initialized.  
For more information on these registers see the device Technical Reference Manual.  
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in  
Table 4-27.  
Table 4-27. Memory Initialization  
ADDRESS RANGE  
CONNECTING MODULE  
MSINENA REGISTER BIT #  
BASE ADDRESS  
0x08000000  
0x08010000  
0x08020000  
0xFF0A0000  
0xFF0C0000  
0xFF0E0000  
0xFF1A0000  
0xFF1C0000  
0xFF1E0000  
0xFF3A0000  
0xFF3E0000  
0xFF440000  
0xFF460000  
0xFF4C0000  
0xFF4E0000  
0xFFF80000  
0xFFF82000  
ENDING ADDRESS  
0x0800FFFF  
0x0801FFFF  
0x0802FFFF  
0xFF0BFFFF  
0xFF0DFFFF  
0xFF0FFFFF  
0xFF1BFFFF  
0xFF1DFFFF  
0xFF1FFFFF  
0xFF3BFFFF  
0xFF3FFFFF  
0xFF57FFFF  
0xFF47FFFF  
0xFF4DFFFF  
0xFF4FFFFF  
0xFFF80FFF  
0xFFF82FFF  
RAM (PD#1)  
RAM (RAM_PD#1)  
RAM (RAM_PD#2)  
MIBSPI5 RAM  
MIBSPI3 RAM  
MIBSPI1 RAM  
DCAN3 RAM  
0(1)  
0(1)  
0(1)  
12(2)  
11(2)  
7(2)  
10  
6
DCAN2 RAM  
DCAN1 RAM  
5
MIBADC2 RAM  
MIBADC1 RAM  
N2HET2 RAM  
N2HET1 RAM  
HET TU2 RAM  
HET TU1 RAM  
DMA RAM  
14  
8
15  
3
16  
4
1
VIM RAM  
2
USB Device RAM  
RAM is not CPU-Addressable  
n/a  
Ethernet RAM (CPPI Memory  
Slave)  
0xFC520000  
0xFC521FFF  
n/a  
(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.  
(2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset..  
This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization  
method. The MibSPIx module must be first brought out of its local reset in order to use the system module auto-initialization method.  
Copyright © 2012, Texas Instruments Incorporated  
System Information and Electrical Specifications  
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Product Folder Links: RM46L450 RM46L850  
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