RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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Table 4-31. EMIF Synchronous Memory Switching Characteristics (continued)
NO.
Parameter
MIN
MAX
Unit
8
toh(CLKH-AIV)
Output hold time, EMIF_CLK rising to
EMIFADDR[12:0] and EMIFBA[1:0]
invalid
1
ns
9
td(CLKH-DV)
Delay time, EMIF_CLK rising to
EMIFDATA[15:0] valid
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
Output hold time, EMIF_CLK rising to
EMIFDATA[15:0] invalid
1
1
1
1
1
Delay time, EMIF_CLK rising to
EMIFnRAS valid
Output hold time, EMIF_CLK rising to
EMIFnRAS invalid
Delay time, EMIF_CLK rising to
EMIFnCAS valid
Output hold time, EMIF_CLK rising to
EMIFnCAS invalid
Delay time, EMIF_CLK rising to
EMIFnWE valid
Output hold time, EMIF_CLK rising to
EMIFnWE invalid
Delay time, EMIF_CLK rising to
EMIFDATA[15:0] tri-stated
Output hold time, EMIF_CLK rising to
EMIFDATA[15:0] driving
94
System Information and Electrical Specifications
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