RM46L450
RM46L850
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SPNS184 –SEPTEMBER 2012
4.15 Vectored Interrupt Manager
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow
of program execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).
4.15.1 VIM Features
The VIM module has the following features:
•
Supports 128 interrupt channels.
Provides programmable priority and enable for interrupt request lines.
–
•
•
Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
Provides two software dispatch mechanisms when the CPU VIC port is not used.
–
–
Index interrupt
Register vectored interrupt
•
Parity protected vector interrupt table against soft errors.
4.15.2 Interrupt Request Assignments
Table 4-32. Interrupt Request Assignments
Modules
Interrupt Sources
Default VIM Interrupt
Channel
ESM
Reserved
RTI
ESM High level interrupt (NMI)
Reserved
0
1
RTI compare interrupt 0
RTI compare interrupt 1
RTI compare interrupt 2
RTI compare interrupt 3
RTI overflow interrupt 0
RTI overflow interrupt 1
RTI timebase interrupt
GIO interrupt A
2
RTI
3
RTI
4
RTI
5
RTI
6
RTI
7
RTI
8
GIO
9
N2HET1
HET TU1
MIBSPI1
LIN
N2HET1 level 0 interrupt
HET TU1 level 0 interrupt
MIBSPI1 level 0 interrupt
LIN level 0 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MIBADC1
MIBADC1
DCAN1
SPI2
MIBADC1 event group interrupt
MIBADC1 sw group 1 interrupt
DCAN1 level 0 interrupt
SPI2 level 0 interrupt
Reserved
Reserved
CRC
CRC Interrupt
ESM
ESM Low level interrupt
Software interrupt (SSI)
PMU Interrupt
SYSTEM
CPU
GIO
GIO interrupt B
N2HET1
HET TU1
MIBSPI1
N2HET1 level 1 interrupt
HET TU1 level 1 interrupt
MIBSPI1 level 1 interrupt
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System Information and Electrical Specifications
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