RM46L450
RM46L850
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SPNS184 –SEPTEMBER 2012
Extended Due to EMIF_WAIT
SETUP
STROBE
STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_DATA[15:0]
14
11
EMIF_nOE
EMIF_WAIT
2
2
Asserted
Deasserted
Figure 4-13. EMIFnWAIT Read Timing Requirements
4.14.2.2 Write Timing (Asynchronous RAM)
15
1
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_nDQM[1:0]
16
17
19
21
23
18
20
24
22
EMIF_nWE
27
26
EMIF_DATA[15:0]
EMIF_nOE
Figure 4-14. Asynchronous Memory Write Timing
Copyright © 2012, Texas Instruments Incorporated
System Information and Electrical Specifications
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