RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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Extended Due to EMIF_WAIT
SETUP
STROBE
STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_DATA[15:0]
28
25
EMIF_nWE
EMIF_WAIT
2
2
Asserted
Deasserted
Figure 4-15. EMIFnWAIT Write Timing Requirements
4.14.2.3 Read Timing (Synchronous RAM)
BASIC SDRAM
1
READ OPERATION
2
2
EMIF_CLK
4
3
5
7
7
EMIF_nCS[0]
6
EMIF_nDQM[1:0]
EMIF_BA[1:0]
8
8
EMIF_ADDR[12:0]
19
20
2 EM_CLK Delay
18
17
EMIF_DATA[15:0]
EMIF_nRAS
11
12
13
14
EMIF_nCAS
EMIF_nWE
Figure 4-16. Basic SDRAM Read Operation
90
System Information and Electrical Specifications
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