RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
www.ti.com
4.13 On-Chip SRAM Initialization and Testing
4.13.1 On-Chip SRAM Self-Test Using PBIST
4.13.1.1 Features
•
•
•
Extensive instruction set to support various memory test algorithms
ROM-based algorithms allow application to run TI production-level memory tests
Independent testing of all on-chip SRAM
4.13.1.2 PBIST RAM Groups
Table 4-26. PBIST RAM Grouping
Test Pattern (Algorithm)
March 13N(1)
two port
(cycles)
March 13N(1)
single port
(cycles)
triple read
slow read
triple read
fast read
Memory
RAM Group
Test Clock
MEM Type
ALGO MASK
0x1
ALGO MASK
0x2
ALGO MASK
0x4
ALGO MASK
0x8
PBIST_ROM
STC_ROM
DCAN1
1
ROM CLK
ROM CLK
VCLK
VCLK
VCLK
HCLK
VCLK
VCLK
VCLK
VCLK
VCLK
HCLK
VCLK
VCLK
VCLK
VCLK
VCLK
HCLK
HCLK
ROM
X
X
X
X
2
ROM
3
Dual Port
Dual Port
Dual Port
Single Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Single Port
Single Port
25200
25200
25200
DCAN2
4
DCAN3
5
ESRAM1
MIBSPI1
MIBSPI3
MIBSPI5
VIM
6
266280
7
33440
33440
33440
12560
4200
8
9
10
11
12
13
14
18
19
20
21
22
23
24
25
26
27
MIBADC1
DMA
18960
31680
6480
N2HET1
HET TU1
MIBADC2
N2HET2
HET TU2
ESRAM5
ESRAM6
4200
31680
6480
266280
266280
8700
6360
Dual Port
ETHERNET
USB
VCLK3
VCLK3
Single Port
Dual Port
133160
66600
4240
Single Port
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
The PBIST ROM clock frequency is limited to 100MHz, if 100MHz < HCLK <= HCLKmax, or HCLK, if
HCLK <= 100MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
86
System Information and Electrical Specifications
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