ADS1259
SBAS424C –JUNE 2009–REVISED MARCH 2010
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SERIAL INTERFACE
DATA INPUT (DIN)
The SPI-compatible serial interface consists of four
signals: CS, SCLK, DIN, and DOUT or three signals,
in which case CS may be tied low. The interface is
used to read conversion data, configure registers,
and control the ADS1259 operation.
DIN is the input data pin and is used with SCLK to
send data to the ADS1259 (opcode commands and
register data). The device latches input data on the
falling edge of SCLK.
DATA OUTPUT (DOUT)
SERIAL COMMUNICATION
DOUT is the output data pin and is used with SCLK
to read conversion and register data from the
ADS1259. In addition to providing data output, in
RDATAC mode DOUT indicates when data are
ready. Data are ready when DOUT transitions low. In
this manner, DOUT functions the same as DRDY
(with CS = 0), as shown in
data, the data are shifted out on the rising edge of
SCLK. DOUT is in a 3-state condition when CS is
high.
The ADS1259 communications occur by clocking
commands into the device (on DIN) and reading
register and conversion data (on DOUT). The SCLK
input is used to clock the data into and out of the
device. CS disables the ADS1259 serial port but
otherwise does not affect the ADC operation. The
communication protocol to the ADS1259 is
half-duplex. That is, data are transmitted to and from
the device one direction at a time.
Figure
56. When reading
Communications to and from the ADS1259 occurs on
8-bit boundaries. If an unintentional SCLK transition
should occur (such as from a possible noise spike),
the ADS1259 serial port may not respond properly.
The port can be reset by one of the following ways:
DATA READY (DRDY)
DRDY is an output that indicates when conversion
data are available for reading (falling edge active).
DRDY is asserted on an output pin and also a
register bit. To poll the DRDY register bit, set the stop
read data continuous mode and then read the
CONFIG2 register. When the DRDY bit is low, data
can be read. The data read operation must complete
within 20 fCLK cycles of the next DRDY falling edge.
After power-on or after reset, DRDY defaults high.
1. Take CS high and then low to reset the interface
2. Hold SCLK low for 216 fCLK cycles to reset the
interface
3. Take RESET/PWDN low and back high to overall
reset the device
4. Cycle the power supplies to overall reset the
device
When reading data in Gate Control mode, DRDY is
reset high on the first SCLK rising edge. If data are
not retrieved, DRDY pulses high during the new data
update time, as shown in Figure 56. Do not retrieve data
during this time as the data are invalid.
CHIP SELECT (CS)
The chip select (CS) selects the ADS1259 for SPI
communication. To select the device, pull CS low. CS
must remain low for the duration of the serial
communication. When CS is taken high, the serial
interface is reset, input commands are ignored, and
In Pulse Control mode, DRDY remains low until a
new conversion is started. The previous conversion
data may be read 20 tCLK prior to the DRDY falling
edge.
DOUT enters
a
high-impedance state. If the
ADS1259 does not share the serial bus with another
device, CS may be tied low. Note that DRDY remains
active when CS is high.
20 tCLK
Data Updating
DRDY Pin(1)(2)
SERIAL CLOCK (SCLK)
The serial clock (SCLK) is a Schmitt-triggered input
used to clock data into and out of the ADS1259. Even
though the input is relatively noise immune, it is
recommended to keep SCLK as clean as possible to
prevent glitches from accidentally shifting the data. If
SCLK is held low for 216 fCLK periods, the serial
interface resets. After reset the next communication
cycle can be started. The timeout can be used to
recover communication when the serial interface is
interrupted. The SPI timeout is enabled by register bit
SPI. When the serial interface is idle, hold SCLK low.
(1) DOUT functions in the same manner as the DRDY pin if CS is
low and in the RDATAC mode.
(2) The DRDY bit functions in the same manner as the DRDY pin
(SDATAC mode only).
Figure 56. DRDY and DOUT With No Data
Retrieval
28
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