ADS1259
SBAS424C –JUNE 2009–REVISED MARCH 2010
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Pulse Control Mode (PULSE Bit = 1)
Settling Time Using START
In the Pulse Control mode, the ADS1259 performs a
single conversion when either the START pin is taken
high or when the START command is sent. As seen
in Figure 51, DRDY goes high when the conversion is
started. When the conversion is complete, DRDY
goes low and further conversions are halted. To start
a new conversion, transition the START pin back to
high, or transmit the START opcode again.
When START goes high (via pin or command) a
delay may be programmed before the conversion
filter cycle begins. The programmable delay may be
useful to provide time for external circuits (such as
after an external signal mux change), before the
reading is started. Register bits DELAY[2:0] set the
initial delay time as shown in Table 8.
Table 8. Initial START Delay
DELAY[2:0]
000
tDELAY (tCLK
)
tDELAY (µs)(1)
START Pin
0
0
OR
OR
001
64
8.68
17.4
34.7
69.4
139
010
128
START
START
011
256
Single
Conversion
Single
Conversion
Halted
Halted
100
512
101
1024
2048
4096
DRDY
110
278
111
556
(1) START opcode command takes effect on the seventh SCLK
falling edge.
(1) fCLK = 7.3728MHz.
Figure 51. Pulse Control Mode
After the programmable delay, the digital filter is reset
and a new conversion is started. DRDY goes low
when data are ready. There is no need to ignore or
discard data; the data are completely settled. The
total time to perform the first conversion is the sum of
the programmable delay time and the settling of the
digital filter. That is, the value of Table 8 and Table 9
combined. Figure 52 shows the timing and Table 9
shows the settling time with programmable delay
equal to '0'.
CONVERSION SETTLING TIME
The ADS1259 features a digital filter architecture in
which settling time can be traded for wide filter
notches, resulting in improved line-cycle rejection.
This trade-off is determined by the selection of the
sinc1 or sinc2 filter. The sinc1 filter settles in a single
cycle while the sinc2 filter provides wide-width filter
notches. The settling time of the ADS1259 is different
if START is used to begin conversions or if the
ADS1259 is free-running the conversions. These
modes are explained in the Settling Time Using
START and Settling Time While Continuously
Converting sections.
Table 9. Settling Time Using START
SETTLING TIME (tSET) (ms)(1)
DATA RATE
(SPS)
10
sinc1
100
sinc2
200
16.6
50
60.3
20.3
17.0
2.85
1.18
0.632
0.424
120
40.4
33.7
5.42
2.10
0.980
0.563
VIN = AINP - AINN
60
Settled VIN
400
START
Pin
1200
3600
14,400
7th Falling SCLK Edge of Opcode
or
START
Command
(1) fCLK = 7.3728MHz, DELAY[2:0] = 000.
(1)
tSET
DRDY
DOUT
Settled
Data
(1) tSET = initial start delay plus the new conversion cycle time.
Figure 52. Data Retrieval Time After START
24
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