ADS1259
SBAS424C –JUNE 2009–REVISED MARCH 2010
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DATA RETRIEVAL
The Read Data Continuous mode is cancelled by
sending the Stop Read Data Continuous command
(SDATAC). This operation occurs simultaneously with
ADC conversion data on DOUT which can be
ignored. Once the SDATAC command is sent, other
commands may be sent to the ADS1259. Observe
the SCLK and DRDY timing requirements, when
reading data in this mode, as shown in Figure 58 and
Table 18.
New conversion data are available when DRDY goes
low. Read the data within 20 fCLK cycles of the next
DRDY falling edge or the data are incorrect. Do not
read data during this interval. The conversion data
may be read in two ways: Data Read in Continuous
mode and Data Read in Stop Continuous mode.
Data Read Operation in Continuous Mode
In Read Data Continuous mode the conversion data
may be shifted out directly without the need of the
data read command. When DRDY (and DOUT, if CS
is low) assert low, the conversion data are ready. The
data are shifted out on DOUT on the rising edges of
SCLK, with the most significant bit (MSB) clocked out
first. In Gate Convert Mode, DRDY returns to high on
the first falling edge of SCLK. In Pulse Convert mode,
DRDY remains low until a new conversion starts.
tDRSC
DRDY
SCLK
tSCDR
Figure 58. SCLK to DRDY Timing
As shown in Figure 59, the conversion data consist of
three or four bytes (data MSB first), depending on
whether the checksum byte is included. The data
may be read multiple times by continuing to shift the
data. The data read operation must be completed
with 20 fCLK cycles of next DRDY falling edge.
Table 18. SCLK and DRDY Timing Characteristics
for Figure 57
SYMBOL
DESCRIPTION
MIN
UNIT
(1)
tSCDR
SCLK low before DRDY
low(1)
20
tCLK
(1)
tDRSC
DRDY falling edge to SCLK
rising edge(1)
40
ns
(1) These requirements apply only to reading conversion data in
RDATAC mode.
Data Ready
Next Data Ready
DRDY(1)
CS(2)
1
9
17
25
33
(4)
tUPDATE
SCLK(3)
DOUT
DIN(8)
Hi-Z
CHECKSUM(6)
DATA MSB(7)
(5)
DATA MSB
DATA MID
DATA LSB
(1) In Gate Convert Conversion mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Convert mode, DRDY remains low
until the next conversion is started.
(2) CS may be held low. If CS is low, DOUT asserts low with DRDY.
(3) Data are updated on the rising edge of SCLK. DOUT is low until the first rising edge of SCLK.
(4) tUPDATE = 20/fCLK. Do not read data during this time.
(5) During this interval, DOUT follows DRDY.
(6) Optional data checksum byte.
(7) Optional repeat of previous conversion data.
(8) Hold DIN low, except for transmission of the SDATAC (STOP Read Data Continuous command).
Figure 59. Data Read Operation in Continuous Mode
30
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