Table 9−15. Smart Card Configuration 1 Register Description
BIT
31−28
27
FIELD NAME
SCRTCH_PAD
CLASS_B_SKT3
TYPE
RW
R
DESCRIPTION
Scratch pad
Socket 3 Class B Smart Card support. Since socket 3 is not implemented in the controller, this
bit is a read-only 0.
26
25
24
23
22
21
20
19
18
17
16
15
14
CLASS_B_SKT2
CLASS_B_SKT1
CLASS_B_SKT0
CLASS_A_SKT3
CLASS_A_SKT2
CLASS_A_SKT1
CLASS_A_SKT0
EMVIF_EN_SKT3
EMVIF_EN_SKT2
EMVIF_EN_SKT1
EMVIF_EN_SKT0
GPIO_EN_SKT3
GPIO_EN_SKT2
RW
RW
RW
R
Socket 2 Class B Smart Card support. Since socket 2 is not implemented in the controller, this
bit is a read-only 0.
Socket 1 Class B Smart Card support. When this bit is set to 1, socket 1 supports Class B Smart
Cards.
Socket 0 Class B Smart Card support. When this bit is set to 1, socket 0 supports Class B Smart
Cards.
Socket 3 Class A Smart Card support. Since socket 3 is not implemented in the controller, this
bit is a read-only 0.
RW
RW
RW
R
Socket 2 Class A Smart Card support. Since socket 2 is not implemented in the controller, this
bit is a read-only 0.
Socket 1 Class A Smart Card support. When this bit is set to 1, socket 1 supports Class A Smart
Cards.
Socket 0 Class A Smart Card support. When this bit is set to 1, socket 0 supports Class A Smart
Cards.
Socket 3 EMV interface enable. Since socket 3 is not implemented in the controller, this bit is
a read-only 0.
RW
RW
RW
R
Socket 2 EMV interface enable. Since socket 2 is not implemented in the controller, this bit is
a read-only 0.
Socket 1 EMV interface enable. When this bit is set to 1, the internal EVM interface for socket
1 is enabled.
Socket 0 EMV interface enable. When this bit is set to 1, the internal EVM interface for socket
0 is enabled.
Socket 3 GPIO enable. Since socket 3 is not implemented in the controller, this bit is a read-only
0.
RW
Socket 2 GPIO enable. Since socket 2 is not implemented in the controller, this bit is a read-only
0.
13
12
11
GPIO_EN_SKT1
GPIO_EN_SKT0
RW
RW
R
Socket 1 GPIO enable. When this bit is set to 1, the SC_GPIOs for socket 1 are enabled.
Socket 0 GPIO enable. When this bit is set to 1, the SC_GPIOs for socket 0 are enabled.
PCMCIA_MODE_SKT3
Socket 3 PCMCIA mode. Since socket 3 is not implemented in the controller, this bit is a
read-only 0.
10
9
PCMCIA_MODE_SKT2
PCMCIA_MODE_SKT1
PCMCIA_MODE_SKT0
PME_SUPPORT_SKT3
PME_SUPPORT_SKT2
R
R
Socket 2 PCMCIA mode. Since socket 2 is not implemented in the controller, this bit is a
read-only 0.
Socket 1 PCMCIA mode. Since socket 1 is implemented as a dedicated socket in the controller,
this bit returns 1 when read.
8
R
Socket 0 PCMCIA mode. Since socket 0 is implemented as a dedicated socket in the controller,
this bit returns 1 when read.
7
R
Socket 3 PME support. Since socket 3 is not implemented in the controller, this bit is a read-only
0.
6
RW
Socket 2 PME support. Since socket 2 is not implemented in the controller, this bit is a read-only
0.
5
4
3
2
1
0
PME_SUPPORT_SKT1
PME_SUPPORT_SKT0
SKT3_EN
RW
RW
R
Socket 1 PME support. When this bit is set to 1, socket 1 card insertions cause a PME event.
Socket 0 PME support. When this bit is set to 1, socket 0 card insertions cause a PME event.
Socket 3 enable. Since socket 3 is not implemented in the controller, this bit is a read-only 0.
Socket 2 enable. Since socket 2 is not implemented in the controller, this bit is a read-only 0.
Socket 1 enable. When this bit is set to 1, socket 1 is enabled.
SKT2_EN
RW
RW
RW
SKT1_EN
SKT0_EN
Socket 0 enable. When this bit is set to 1, socket 0 is enabled.
9−16
TI [ TEXAS INSTRUMENTS ]
