5.11 Buffer Control Register
The buffer control register allows software to enable/disable write posting and control memory read burst prefetching.
The buffer control register also enables/disables the posted memory write reconnect feature. See Table 5–9 for a
complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Buffer control
R
0
R
0
R
0
R/W
0
R
0
R/W
1
R/W
1
R/W
1
Register:
Type:
Buffer control
Read-only, Read/Write
Offset:
Default:
59h
07h
Table 5–9. Buffer Control Register
BIT
TYPE
FUNCTION
7–5
R
Reserved. Bits 7 through 5 return 0s when read.
Upstream MRM/MRL read burst enable. By default, the PCI2250 is set to memory read burst a single cache line. By setting
this bit to 1, the PCI2250 will memory read burst multiple cache lines or until the FIFO is full. To utilize this feature, bit 4 of
the chip control register (offset 40h, see Section 5.1) must be set to 0.
4
R/W
0 = Disabled (default)
1 = Enabled
3
2
R
Reserved. Bit 3 returns 0 when read.
Downstream memory read burst enable. The bridge defaults to downstream memory read bursting enabled. Bit 2 enables
downstream memory read bursting in prefetchable windows. This bit is encoded as:
R/W
0 = Disabled
1 = Enabled (default)
Secondary-to-primary write posting enable. Enables posting of write data to and from the primary interface. If bit 1 is not
set, the bridge must drain any data in its buffers before accepting data to or from the primary interface. Each data word must
then be accepted by the target before the bridge can accept the next word from the source master. The bridge must not
release the source master until the last word is accepted by the target. Operating with the write posting enabled enhances
system performance.
1
0
R/W
R/W
0 = Write posting disabled
1 = Write posting enabled (default)
Primary-to-secondary write posting enable. Enables posting of write data to and from the secondary interface. If bit 0 is not
set, then the bridge must drain any data in its buffers before accepting data to or from the secondary interface. Each data
word must then be accepted by the target before the bridge can accept the next word from the source master. The bridge
must not release the source master until the last word is accepted by the target. Operating with the write posting enabled
enhances system performance.
0 = Write posting disabled
1 = Write posting enabled (default)
5–9
TI [ TEXAS INSTRUMENTS ]
