3.14.2 PCI Clock Run Feature
The PCI2250 supports the PCI clock run protocol when in clock run mode, as defined in the PCI Mobile Design Guide.
When the system’s central resource signals to the system that it wants to stop the PCI clock (P_CLK) by driving the
primary clock run (P_CLKRUN) signal high, the bridge either signals that it is OK to stop the PCI clock by leaving
P_CLKRUN deasserted (high) or signals to the system to keep the clock running by driving P_CLKRUN low.
The PCI2250 clock run control register provides a clock run enable bit for the primary bus and a separate clock run
enable bit for the secondary bus. The bridge’s P_CLKRUN and secondary clock run (S_CLKRUN) features are
enabled by setting bits 3 and 1, respectively, in the clock run control register (offset 5Bh, see Section 5.13). Bit 2 of
the clock run control register allows software to enable the bridge’s keep clock running mode to prevent the system
from stopping the primary PCI clock. There are two conditions for restarting the secondary clock: a downstream
transaction restarts the secondary clock or S_CLKRUN is asserted.
Two clock run modes are supported on the secondary bus. The bridge can be configured to stop the secondary PCI
clock only in response to a request from the primary bus to stop the clock, or it can be configured to stop the secondary
clock whenever the secondary bus is idle and there are no transaction requests from the primary bus, regardless of
the primary clock (see Section 5.13, Clock Run Control Register).
3.15 PCI Power Management
The PCI Power Management Interface Specification establishes the infrastructure required to let the operating
systemcontrolthepowerofPCIfunctions. ThisisdonebydefiningastandardPCIinterfaceandoperationstomanage
the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software visible
power management states, which result in varying levels of power savings.
The four power management states of PCI functions are D0—fully on state, D1 and D2—intermediate states, and
D3—off state. Similarly, bus power states are B0–B3. The bus power states B0–B3 are derived from the device power
state of the originating device. The power state of the secondary bus is derived from the power state of the PCI2250.
For the operating system to manage the device power states on the PCI bus, the PCI function supports four power
management operations:
•
•
•
•
Capabilities reporting
Power status reporting
Setting the power state
System wake–up
The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The
presence of the new capabilities list is indicated by a bit in the status register (offset 06h, see Section 4.4) which
provides access to the capabilities list.
3.15.1 Behavior in Low Power States
The PCI2250 supports D0, D1, D2, and D3
power states when in TI mode. The PCI2250 only supports D0 and
hot
D3 power states when in Intel mode. The PCI2250 is fully functional only in the D0 state. In the lower power states,
hot
the bridge does not accept any I/O or memory transactions. These transactions are aborted by the master. The bridge
accepts type 0 configuration cycles in all power states. The bridge also accepts type 1 configuration cycles but does
not pass these cycles to the secondary bus in any of the low power states. Type 1 configuration writes are discarded
and reads return all 1s. All error reporting is done in the low power states. When in D2 and D3 states, the bridge
hot
turns off all secondary clocks for further power savings when in TI mode or if BPCC is pulled high in the Intel mode.
When going from D3
to D0, an internal reset is generated. This reset initializes all PCI configuration registers to
hot
their default values. All TI extension registers (40h–FFh) are not reset. The power management registers (offset E0h)
are also not reset.
3–10
TI [ TEXAS INSTRUMENTS ]
