P_SERR event disable register occur and that condition is enabled. By default, all error conditions are enabled in the
P_SERR event disable register. When the bridge signals SERR, bit 14 of the secondary status register (offset 1Eh,
see Section 4.19) is set.
3.9.1 Posted Write Parity Error
If bit 1 in the P_SERR event disable register (offset 64h, see Section 5.18) is 0, then parity errors on the target bus
during a posted write are passed to the initiating bus as an SERR. When this occurs, bit 1 of the P_SERR status
register (offset 6Ah, see Section 5.20) is set. The status bit is cleared by writing a 1.
3.9.2 Posted Write Timeout
If bit 2 in the P_SERR event disable register (offset 64h, see Section 5.18) is 0 and the retry timer expires while
attempting to complete a posted write, then the PCI2250 signals SERR on the initiating bus. When this occurs, bit 2
of the P_SERR status register (offset 6Ah, see Section 5.20) is set. The status bit is cleared by writing a 1.
3.9.3 Target Abort on Posted Writes
Ifbit3intheP_SERReventdisableregister(offset 64h, see Section 5.18) is 0 and the bridge gets a target abort during
a posted write transaction, then the PCI2250 signals SERR on the initiating bus. When this occurs, bit 3 of the
P_SERR status register (offset 6Ah, see Section 5.20) is set. The status bit is cleared by writing a 1.
3.9.4 Master Abort on Posted Writes
If bit 4 in the P_SERR event disable register (offset 64h, see Section 5.18) is 0 and a posted write transaction results
in a master abort, then the PCI2250 signals SERR on the initiating bus. When this occurs, bit 4 of the P_SERR status
register (offset 6Ah, see Section 5.20) is set. The status bit is cleared by writing a 1.
3.9.5 Master Delayed Write Timeout
If bit 5 in the P_SERR event disable register (offset 64h, see Section 5.18) is 0 and the retry timer expires while
attempting to complete a delayed write, then the PCI2250 signals SERR on the initiating bus. When this occurs, bit 5
of the P_SERR status register (offset 6Ah, see Section 5.20) is set. The status bit is cleared by writing a 1.
3.9.6 Master Delayed Read Timeout
If bit 6 in the P_SERR event disable register (offset 64h, see Section 5.18) is 0 and the retry timer expires while
attempting to complete a delayed read, then the PCI2250 signals SERR on the initiating bus. When this occurs, bit 6
of the P_SERR status register (offset 6Ah, see Section 5.20) is set. The status bit is cleared by writing a 1.
3.9.7 Secondary SERR
The PCI2250 passes SERR from the secondary bus to the primary bus if it is enabled for SERR response (bit 8 in
the command register is 1) and bit 1 in the bridge control register (offset 3Eh, see Section 4.32) is set.
3.10 Parity Handling and Parity Error Reporting
The PCI2250 can be configured to pass parity or provide parity via bit 14 of the diagnostic control register (offset 5Ch,
see Section 5.14). When this bit is cleared to 0, the bridge is enabled for passing parity errors. Parity error passing
is the default mode in the bridge. The following parity conditions result in the bridge signaling an error.
3.10.1 Address Parity Error
If the parity error response bit (bit 6) in the command register (offset 04h, see Section 4.3) is set, then the PCI2250
signals SERR on address parity errors and target abort transactions.
3–7
TI [ TEXAS INSTRUMENTS ]
