ONET1131EC
ZHCSFG0 –SEPTEMBER 2016
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7.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
Figure 27. Core Level Register 2
7
6
5
4
3
2
1
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. Core Level Register 2 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
0
Reserved
7.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
Figure 28. Core Level Register 3
7
6
5
4
3
2
1
0
ADCEN
R/W
OSCEN
R/W
Reserved
R/W
ADCRST
R/W
Reserved
R/W
ADCSEL2
R/W
ADCSEL1
R/W
ADCSEL0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Core Level Register 3 Field Descriptions
Bit
Field
Type
Reset
Description
ADC enabled bit
1 = ADC enabled
0 = ADC disabled
7
ADCEN
R/W
0h
ADC oscillator bit
6
5
4
OSCEN
R/W
R/W
R/W
0h
0h
0h
1 = Oscillator enabled
0 = Oscillator disabled
Reserved
ADCRST
Reserved
ADC reset
1 = ADC reset
0 = ADC no reset
3
2
1
Reserved
ADCSEL2
ADCSEL1
R/W
R/W
R/W
0h
0h
0h
Reserved
ADC input selection bits <2:0>
000 selects the temperature sensor
001 selects the power supply monitor
010 selects IMONB
0
ADCSEL0
R/W
0h
011 selects IMONP
1XX are reserved
24
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