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7.6 Register Mapping
7.6.1 R/W Control Registers
7.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
Figure 25. Core Level Register 0
7
6
5
4
3
2
1
0
GLOBAL SW_PIN RESET
RWSC
Reserved
I2C RESET
RWSC
EN_CHIP
RW
RW
RWSC
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset. RWSC = Read/Write self clearing (always reads back to zero)
Table 2. Core Level Register 0 Field Descriptions
Bit
Field
Type
Reset
Description
Global Reset SW
7
GLOBAL SW_PIN RESET
Reserved
RWSC
0
1 = reset, resets all I2C and EEPROM modules to default
0 = normal operation (self-clearing, always reads back ‘0’)
6:3
2
R/W
1
0
Reserved
Reserved
RWSC
Chip reset bit
1
0
I2C RESET
EN_CHIP
RWSC
R/W
0
1
1 = resets all I2C registers to default
0 = normal operation (self-clearing, always reads back ‘0’)
Enable chip bit
1 = Chip enabled
0 = Chip disabled
22
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