OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-7. C674x DSP Interrupt Controller Registers
BYTE ADDRESS
0x0180 0000
0x0180 0004
0x0180 0008
0x0180 000C
0x0180 0020
0x0180 0024
0x0180 0028
0x0180 002C
0x0180 0040
0x0180 0044
0x0180 0048
0x0180 004C
0x0180 0080
0x0180 0084
0x0180 0088
0x0180 008C
0x0180 00A0
0x0180 00A4
0x0180 00A8
0x0180 00AC
0x0180 00C0
0x0180 00C4
0x0180 00C8
0x0180 00CC
0x0180 00E0
0x0180 00E4
0x0180 00E8
0x0180 00EC
0x0180 0104
0x0180 0108
0x0180 010C
0x0180 0140 - 0x0180 0144
0x0180 0180
0x0180 0184
0x0180 0188
0x0180 01C0
REGISTER NAME
EVTFLAG0
EVTFLAG1
EVTFLAG2
EVTFLAG3
EVTSET0
DESCRIPTION
Event flag register 0
Event flag register 1
Event flag register 2
Event flag register 3
Event set register 0
EVTSET1
Event set register 1
EVTSET2
Event set register 2
EVTSET3
Event set register 3
EVTCLR0
Event clear register 0
EVTCLR1
Event clear register 1
EVTCLR2
Event clear register 2
EVTCLR3
Event clear register 3
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
MEVTFLAG0
MEVTFLAG1
MEVTFLAG2
MEVTFLAG3
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
INTMUX1
Event mask register 0
Event mask register 1
Event mask register 2
Event mask register 3
Masked event flag register 0
Masked event flag register 1
Masked event flag register 2
Masked event flag register 3
Exception mask register 0
Exception mask register 1
Exception mask register 2
Exception mask register 3
Masked exception flag register 0
Masked exception flag register 1
Masked exception flag register 2
Masked exception flag register 3
Interrupt mux register 1
Interrupt mux register 2
Interrupt mux register 3
Reserved
INTMUX2
INTMUX3
-
INTXSTAT
INTXCLR
Interrupt exception status
Interrupt exception clear
Dropped interrupt mask register
Event assert register
INTDMASK
EVTASRT
6.7.3 ARM/DSP Communications Interrupts
Communications Interrupts between the ARM and DSP are part of the SYSCFG module on the
OMAP-L13x family of devices.( Section 4.5.1 CHIPSIG, Section 4.5.2 CHIPSIG_CLR)
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