OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
6.7.2 DSP Interrupts
The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 6-6. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-7
summarizes the C674x interrupt controller registers and memory locations.
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Peripheral Information and Electrical Specifications
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