OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
6.9 EDMA
Table 6-12 is the list of EDMA3 Channel Contoller Registers and Table 6-13 is the list of EDMA3 Transfer
Controller registers.
Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
0x01C0 0000
Acronym
PID
Register Description
Peripheral Identification Register
EDMA3CC Configuration Register
0x01C0 0004
CCCFG
Global Registers
0x01C0 0200
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0240
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0260
0x01C0 0284
0x01C0 0300
0x01C0 0308
0x01C0 0310
0x01C0 0314
0x01C0 0318
0x01C0 031C
0x01C0 0320
0x01C0 0340
0x01C0 0348
0x01C0 0350
0x01C0 0358
0x01C0 0380
0x01C0 0384
0x01C0 0388
0x01C0 038C
0x01C0 0400 - 0x01C0 043C
0x01C0 0440 - 0x01C0 047C
0x01C0 0600
0x01C0 0604
0x01C0 0620
0x01C0 0640
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
QDMAQNUM
QUEPRI
QDMA Channel 0 Mapping Register
QDMA Channel 1 Mapping Register
QDMA Channel 2 Mapping Register
QDMA Channel 3 Mapping Register
QDMA Channel 4 Mapping Register
QDMA Channel 5 Mapping Register
QDMA Channel 6 Mapping Register
QDMA Channel 7 Mapping Register
DMA Channel Queue Number Register 0
DMA Channel Queue Number Register 1
DMA Channel Queue Number Register 2
DMA Channel Queue Number Register 3
QDMA Channel Queue Number Register
Queue Priority Register(1)
EMR
Event Missed Register
EMCR
Event Missed Clear Register
QEMR
QDMA Event Missed Register
QEMCR
QDMA Event Missed Clear Register
EDMA3CC Error Register
CCERR
CCERRCLR
EEVAL
EDMA3CC Error Clear Register
Error Evaluate Register
DRAE0
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
Event Queue Entry Registers Q0E0-Q0E15
Event Queue Entry Registers Q1E0-Q1E15
Queue 0 Status Register
DRAE1
DRAE2
DRAE3
QRAE0
QRAE1
QRAE2
QRAE3
Q0E0-Q0E15
Q1E0-Q1E15
QSTAT0
QSTAT1
Queue 1 Status Register
QWMTHRA
CCSTAT
Queue Watermark Threshold A Register
EDMA3CC Status Register
Global Channel Registers
0x01C0 1000
0x01C0 1008
ER
Event Register
ECR
Event Clear Register
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC
memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
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Peripheral Information and Electrical Specifications
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