OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
www.ti.com
Table 6-6. OMAP-L137 DSP Interrupts
EVT#
0
Interrupt Name
EVT0
Source
C674x Int Ctl 0
1
EVT1
C674x Int Ctl 1
2
EVT2
C674x Int Ctl 2
3
EVT3
C674x Int Ctl 3
4
T64P0_TINT12
SYSCFG_CHIPINT2
-
Timer64P0 - TINT12
SYSCFG_CHIPSIG Register
Reserved
5
6
7
EHRPWM0
TPCC0_INT1
EMU-DTDMA
EHRPWM0TZ
EMU-RTDXRX
EMU-RTDXTX
IDMAINT0
HiResTimer/PWM0 Interrupt
TPCC0 Region 1 Interrupt
C674x-ECM
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
HiResTimer/PWM0 Trip Zone Interrupt
C674x-RTDX
C674x-RTDX
C674x-EMC
IDMAINT1
C674x-EMC
MMCSD_INT0
MMCSD_INT1
-
MMCSD MMC/SD Interrupt
MMCSD SDIO Interrupt
Reserved
EHRPWM1
USB0_INT
USB1_HCINT
USB1_RWAKEUP
-
HiResTimer/PWM1 Interrupt
USB0 Interrupt
USB1 OHCI Host Controller Interrupt
USB1 Remote Wakeup Interrupt
Reserved
EHRPWM1TZ
EHRPWM2
EHRPWM2TZ
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
UHPI_DSPINT
-
HiResTimer/PWM1 Trip Zone Interrupt
HiResTimer/PWM2 Interrupt
HiResTimer/PWM2 Trip Zone Interrupt
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
UHPI DSP Interrupt
Reserved
IIC0_INT
I2C0
SP0_INT
SPI0
UART0_INT
-
UART0
Reserved
T64P1_TINT12
GPIO_B1INT
IIC1_INT
Timer64P1 Interrupt 12
GPIO Bank 1 Interrupt
I2C1
SPI1_INT
SPI1
-
Reserved
ECAP0
ECAP0
UART_INT1
UART1
92
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
TI [ TEXAS INSTRUMENTS ]
