OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-6. OMAP-L137 DSP Interrupts (continued)
EVT#
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Interrupt Name
ECAP1
Source
ECAP1
T64P1_TINT34
GPIO_B2INT
-
Timer64P1 Interrupt 34
GPIO Bank 2 Interrupt
Reserved
ECAP2
ECAP2
GPIO_B3INT
EQEP1
GPIO Bank 3 Interrupt
EQEP1
GPIO_B4INT
EMIFA_INT
GPIO Bank 4 Interrupt
EMIFA
EDMA3_CC0_ERRINT
EDMA3_TC0_ERRINT
EDMA3_TC1_ERRINT
GPIO_B5INT
EMIFB_INT
EDMA3 Channel Controller 0
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
GPIO Bank 5 Interrupt
EMIFB Memory Error Interrupt
McASP0,1,2 Combined RX/TX Interrupts
GPIO Bank 6 Interrupt
RTC Combined
MCASP_INT
GPIO_B6INT
RTC_IRQS
T64P0_TINT34
GPIO_B0INT
-
Timer64P0 Interrupt 34
GPIO Bank 0 Interrupt
Reserved
SYSCFG_CHIPINT3
EQEP0
SYSCFG_CHIPSIG Register
EQEP0
UART2_INT
UART2
PSC0_ALLINT
PSC1_ALLINT
GPIO_B7INT
LCDC_INT
PSC0
PSC1
GPIO Bank 7 Interrupt
LDC Controller
PROTERR
SYSCFG Protection Shared Interrupt
Reserved
-
-
Reserved
-
Reserved
T64P0_CMPINT0
T64P0_CMPINT1
T64P0_CMPINT2
T64P0_CMPINT3
T64P0_CMPINT4
T64P0_CMPINT5
T64P0_CMPINT6
T64P0_CMPINT7
T64P1_CMPINT0
T64P1_CMPINT1
T64P1_CMPINT2
T64P1_CMPINT3
T64P1_CMPINT4
T64P1_CMPINT5
T64P1_CMPINT6
T64P1_CMPINT7
Timer64P0 - Compare 0
Timer64P0 - Compare 1
Timer64P0 - Compare 2
Timer64P0 - Compare 3
Timer64P0 - Compare 4
Timer64P0 - Compare 5
Timer64P0 - Compare 6
Timer64P0 - Compare 7
Timer64P1 - Compare 0
Timer64P1 - Compare 1
Timer64P1 - Compare 2
Timer64P1 - Compare 3
Timer64P1 - Compare 4
Timer64P1 - Compare 5
Timer64P1 - Compare 6
Timer64P1 - Compare 7
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