欢迎访问ic37.com |
会员登录 免费注册
发布采购

DP83840AVCE 参数 Datasheet PDF下载

DP83840AVCE图片预览
型号: DP83840AVCE
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100 Mb / s的以太网物理层 [10/100 Mb/s Ethernet Physical Layer]
分类和应用: 电信集成电路电信电路信息通信管理以太网局域网(LAN)标准
文件页数/大小: 91 页 / 682 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号DP83840AVCE的Datasheet PDF文件第2页浏览型号DP83840AVCE的Datasheet PDF文件第3页浏览型号DP83840AVCE的Datasheet PDF文件第4页浏览型号DP83840AVCE的Datasheet PDF文件第5页浏览型号DP83840AVCE的Datasheet PDF文件第7页浏览型号DP83840AVCE的Datasheet PDF文件第8页浏览型号DP83840AVCE的Datasheet PDF文件第9页浏览型号DP83840AVCE的Datasheet PDF文件第10页  
2.0 Pin Description  
The DP83840A pins are classified into the following interface categories (each interface is described in the sections that  
follow):  
MII INTERFACE  
LED INTERFACE  
100 Mb/s SERIAL PMD INTERFACE  
10 Mb/s INTERFACE  
IEEE 1149.1 INTERFACE  
PHY ADDRESS INTERFACE  
MISCELLANEOUS PINS  
POWER AND GROUND PINS  
SPECIAL CONNECT PINS  
CLOCK INTERFACE  
DEVICE CONFIGURATION INTERFACE  
2.1 MII INTERFACE  
Signal Name  
Type  
Pin #  
Description  
TX_CLK  
O, Z  
82  
TRANSMIT CLOCK: Transmit clock outt rom thP83840
25 MHz nibble transmit clock derived from ck GeneModule's (CGM) PLL  
in 100BASE-TX mode  
2.5 MHz transmit clock in 10BASmode  
10 MHz transmit clock in 10BASal mode  
TXD[3]  
TXD[2]  
TXD[1]  
TXD[0]  
I, J  
75  
76  
77  
78  
TRANSMIT DATA: Tramit daMII input ins that accept nibble data during  
normal nibble-wide MII opation aeither 5 MHz (10BASE-T mode) or 25MHz  
(100BASE-X mode)  
In 10 Mb/s serial TXD[pin is used as the serial data input pin. TXD[3:1]  
are ignored.  
TX_EN  
I, J  
I, J  
74  
TRANSMIT ENhigh input indicates the presence of valid nibble data  
on TXD[3:0] for bs or 10 Mb/s nibble mode.  
In 10 Mb/s serial modeactive high indicates the presence of valid 10 Mb/s data on  
TX0].  
TX_ER  
73  
TRANSMIT ERRR: In 100 Mb/s mode, when this signal is high and TX_EN is  
ive the HALsymbol is substituted for the actual data nibble.  
(TXD[4])  
Mb/s mode, this input is ignored.  
der bypass mode (BP_4B5B or BP_ALIGN), TX_ER becomes the TXD [4]  
e new MSB for the transmit 5-bit data word.  
MDC  
72  
67  
ANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management  
data input/output serial interface which may be asynchronous to transmit and  
receive clocks. The maximum clock rate is 2.5 MHz. There is no minimum clock  
rate.  
MDIO  
MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that  
may be sourced by the station management entity or the PHY. This pin requires a  
1.5kpullup resistor.  
I = TTL/CMOS input  
O = TTL/CMOS output  
Z = TRI-STATE output  
J = IEEE 1149.1 pin  
Version A  
National Semiconductor  
Subject to change without notice.  
5
 复制成功!