2.0 Pin Connection Diagram
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
BPSCR
OSCIN
LOWPWR
RES_0
RD+
80
79
78
77
IOGND6
2
IOV
CC6
3
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TX_EN
TX_ER
MDC
4
5
76
75
74
73
72
71
70
6
RD-
7
SD-
8
SD+
9
ANAV
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ANAGND
CRMGND
PCSGND
PCSV
CC
CRMV
69
IOGNDS
IOV
CC
NC
NC
68
67
66
CC5
DP83840AVCE
MDIO
10/100BASE-X ETHERNET PHYSICAL LAYER
ECLV
CRS / PHYAD[2]
COL
CC
TD-
65
64
63
62
TD+
RX_DV
100 -PIN JEDEC METRIC PQFP
RXV
RX_ER / PHYAD[4]
RX_CLK
CC
RXGND
RXI-
61
60
RCLKGND
IOGND4
RXI+
TDV
59
58
57
56
IOV
CC
CC4
TXS-
TXS+
RXD[0]
RXD[1]
TXU-
RXD[2]
TXU+
RXD[3]
55
54
53
52
51
TDGND
RTX
SPEED_10
ENCSEL / PHYAD[1]
IOGND3
REQ
PLLGND
IOV
CC3
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FIGURE 1. DP83840A Pin Connection Diagram
Version A
National Semiconductor
4
Subject to change without notice.
TI [ TEXAS INSTRUMENTS ]
