DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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BUFFER
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL
RESET
REL.
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
BALL
RESET
STATE [9]
MODE
[6]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [7] DSIS [8]
POWER [11]
HYS [12]
TYPE [13]
STATE [10]
AK15
AL15
AL17
AK17
AK20
AL20
AL21
AJ25
AA20
AL30
AL26
F30
DDR[0]_DQS[1]
DDR[0]_DQS[1]
NA /
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
0x01
I/O
I/O
I/O
I/O
I/O
I/O
O
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
H
1
DVDD_DDR[0]
DDR[0]_DQS[1]
DDR[0]_DQS[2]
DDR[0]_DQS[2]
DDR[0]_DQS[3]
DDR[0]_DQS[3]
DDR[0]_ODT[0]
DDR[0]_RAS
DDR[0]_DQS[1]
DDR[0]_DQS[2]
DDR[0]_DQS[2]
DDR[0]_DQS[3]
DDR[0]_DQS[3]
DDR[0]_ODT[0]
DDR[0]_RAS
NA /
NA
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
L
0
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
VDDS_OSC0_1P8
NA /
NA
L
0
NA /
NA
H
H
L
1
NA /
NA
1
NA /
NA
0
NA /
NA
L
0
NA /
NA
O
H
L
1
DDR[0]_RST
DDR[0]_RST
NA /
NA
O
0
DDR[0]_VTP
DDR[0]_VTP
NA /
NA
I
NA
H
NA
NA
1
DDR[0]_WE
DDR[0]_WE
NA /
NA
O
DEVOSC_MXI
DEV_CLKIN
NA /
NA
0x01
0x01
0x01
I
NA
NA
NA
NA
DEVOSC_MXI
DEVOSC_MXO
I
G31
U28
DEVOSC_MXO
DEVOSC_WAKE
NA /
NA
NA
O
NA
H
NA
H
VDDS_OSC0_1P8
DVDD_SD
DEVOSC_WAKE
SPI[1]_SCS[1]
TIM5_IO
PINCNTL7 /
0x4814 0818
0x000E 0000
0x01
0x02
0x40
0x80
NA
I
1
I/O
I/O
I/O
PWR
1
PIN
PIN
NA
GP1[7]
D16, E17, F16, L5, DVDD
M4, M6, M7, N10,
DVDD
NA /
NA
NA
NA
NA
NA
N11, T26, T28, U27
D12, E13, F12,
G12, G13
DVDD_C
DVDD_C
NA /
NA
NA
NA
NA
NA
PWR
PWR
NA
NA
NA
NA
NA
NA
NA
NA
AB14, AB15, AB17, DVDD_DDR[0]
AB18, AC15, AC17,
DVDD_DDR[0]
NA /
NA
AC18, AE15, AE16,
AF16, AG15, AH16
R5, R7, T4, T6, T7 DVDD_GPMC
DVDD_GPMC
DVDD_RGMII
DVDD_SD
NA /
NA
NA
NA
NA
NA
NA
NA
PWR
PWR
PWR
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
W5, W7, Y4, Y6, Y7 DVDD_RGMII
NA /
NA
T25, U25
DVDD_SD
NA /
NA
38
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