DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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BUFFER
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL
RESET
REL.
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
BALL
RESET
STATE [9]
MODE
[6]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [7] DSIS [8]
POWER [11]
HYS [12]
TYPE [13]
STATE [10]
M3
GPMC_A[18]
GPMC_A[18]
PINCNTL107 /
0x4814 09A8
0x0004 0000
0x0004 0000
0x0006 0000
0x0004 0000
0x0006 0000
0x01
O
PIN
PIN
PIN
PIN
PIN
PIN
PIN
1
L
L
DVDD_GPMC
TIM2_IO
0x40
0x80
0x01
0x40
0x80
0x01
0x04
0x80
0x01
0x04
0x80
0x01
0x04
0x10
0x40
0x80
0x01
0x04
0x10
0x40
0x80
0x01
0x02
0x40
0x80
0x01
0x02
0x20
0x40
0x80
0x01
0x02
0x20
0x40
0x80
I/O
I/O
O
GP1[13]
M5
N9
N1
N2
GPMC_A[19]
GPMC_A[20]
GPMC_A[21]
GPMC_A[22]
GPMC_A[19]
TIM3_IO
PINCNTL108 /
0x4814 09AC
L
L
DVDD_GPMC
DVDD_GPMC
DVDD_GPMC
DVDD_GPMC
I/O
I/O
O
GP1[14]
GPMC_A[20]
SPI[2]_SCS[1]
GP1[15]
PINCNTL109 /
0x4814 09B0
H
L
H
L
I/O
I/O
O
PIN
PIN
PIN
PIN
PIN
PIN
1
GPMC_A[21]
SPI[2]_D[0]
GP1[16]
PINCNTL110 /
0x4814 09B4
I/O
I/O
O
GPMC_A[22]
SPI[2]_D[1]
HDMI_CEC
TIM4_IO
PINCNTL111 /
0x4814 09B8
H
H
I/O
I/O
I/O
I/O
O
PIN
PIN
PIN
1
GP1[17]
R8
GPMC_A[23]
GPMC_A[23]
SPI[2]_SCLK
HDMI_HPDET
TIM5_IO
PINCNTL112 /
0x4814 09BC
0x0004 0000
L
L
DVDD_GPMC
I/O
I
0
I/O
I/O
O
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
GP1[18]
AA10
Y11
GPMC_ADV_ALE
GPMC_BE[1]
GPMC_ADV_ALE
GPMC_CS[6]
TIM5_IO
PINCNTL128 /
0x4814 09FC
0x0006 0000
0x0004 0000
H
L
H
L
DVDD_GPMC
DVDD_GPMC
O
I/O
I/O
O
GP1[28]
GPMC_BE[1]
GPMC_A[24]
EDMA_EVT1
TIM7_IO
PINCNTL132 /
0x4814 0A0C
O
I
I/O
I/O
O
GP1[30]
Y3
GPMC_BE[0]_CLE
GPMC_BE[0]_CLE
GPMC_A[25]
EDMA_EVT2
TIM6_IO
PINCNTL131 /
0x4814 0A08
0x0004 0000
L
L
DVDD_GPMC
O
I
I/O
I/O
GP1[29]
42
Device Pins
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