DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources (continued)
Cortex-A8
INTERRUPT NUMBER
ACRONYM
SOURCE
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116-119
120
121
122
123
124
125
126
127
GPIOINT1B
GPIO1
GPMCINT
GPMC
DDRERR
DDR
–
Reserved
HDVICPCONT1SYNC
HDVICP2
HDVICPCONT2SYNC
HDVICP2
–
Reserved
–
IVA0MBOXINT
–
Reserved
HDVICP2 Mailbox
Reserved
–
Reserved
–
Reserved
–
Reserved
TCERRINT0
TCERRINT1
TCERRINT2
TCERRINT3
–
EDMA TC 0 Error
EDMA TC 1 Error
EDMA TC 2 Error
EDMA TC 3 Error
Reserved
SMRFLX_ARM
SMRFLX_CORE
–
SmartReflex ARM Domain
SmartReflex CORE Domain
Reserved
MCMMUINT
DMMINT
SPIINT1
SPIINT2
SPIINT3
Media Controller
DMM
SPI1
SPI2
SPI3
Copyright © 2013, Texas Instruments Incorporated
Power, Reset, Clocking, and Interrupts
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