DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Table 7-25. Maximum Module Clock Frequencies (continued)
MAX FREQUENCY
OPP100 (MHz)
MODULE
CLOCK SOURCE(S)
L3 Medium
L3 Slow
L4 Fast
SYSCLK4
SYSCLK6
SYSCLK4
SYSCLK6
SYSCLK6
SYSCLK6
220
110
220
110
110
110
L4 Slow
Mailbox
McASP
SYSCLK20
SYSCLK21
McASP0/1 AUX_CLK
192
Media Controller
MMCSD0/1/2
OCMC RAM
PLL_MEDIACTL
SYSCLK8
400
192
220
100
SYSCLK4
PCIe SERDES
SERDES_CLKx Pins
DEV Clock
SERDES_CLKx Pins
SERDES
20 or 100
SmartReflex
SPI0/1/2/3
Spinlock
DEV Clock
SYSCLK10
SYSCLK6
SYSCLK18
30
48
110
Sync Timer
Fixed 0.032768
SYSCLK18
DEV Clock
AUX Clock
AUD_CLK0/1/2
TCLKIN
TIMER1/2/3/4/5/6/7/8
30
UART0/1/2
USB
SYSCLK10
48
PLL_USB CLKDCO
Fixed 960
RTCDIVIDER
RCOSC32K
WDT0
Fixed 0.032768
158
Power, Reset, Clocking, and Interrupts
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