DM385, DM388
www.ti.com
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
8.4 EDMA
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses, user-
programmed data transfers, and host accesses.
8.4.1 EDMA Channel Synchronization Events
The EDMA channel controller supports up to 64 channels which service peripherals and memory. Each
EDMA channel is mapped to a default EDMA synchronization event as shown in Table 8-2. In addition,
each EDMA channel can alternatively be mapped to one of the 31 multiplexed EDMA synchronization
events shown in Table 8-3. The EVT_MUX_x registers in the Control Module are used to select between
the default event and the multiplexed events for each channel.
For more detailed information on the EDMA module and how EDMA events are enabled, captured,
processed, linked, chained, cleared, and more, see the Enhanced Direct Memory Access Controller
chapter in the device-specific Technical Reference Manual.
Table 8-2. EDMA Default Synchronization Events
EVENT
NUMBER
DEFAULT
EVENT NAME
DEFAULT EVENT DESCRIPTION
0-1
2
–
SDTXEVT1
SDRXEVT1
–
Reserved
SD1 Transmit
SD1 Receive
Reserved
3
4-7
8
AXEVT0
McASP0 Transmit
McASP0 Receive
McASP1 Transmit
McASP1 Receive
Reserved
9
AREVT0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32-35
36
37
38
AXEVT1
AREVT1
–
–
Reserved
–
Reserved
–
Reserved
SPI0XEVT0
SPI0REVT0
SPI0XEVT1
SPI0REVT1
SPI0XEVT2
SPI0REVT2
SPI0XEVT3
SPI0REVT3
SDTXEVT0
SDRXEVT0
UTXEVT0
URXEVT0
UTXEVT1
URXEVT1
UTXEVT2
URXEVT2
–
SPI0 Transmit 0
SPI0 Receive 0
SPI0 Transmit 1
SPI0 Receive 1
SPI0 Transmit 2
SPI0 Receive 2
SPI0 Transmit 3
SPI0 Receive 3
SD0 Transmit
SD0 Receive
UART0 Transmit
UART0 Receive
UART1 Transmit
UART1 Receive
UART2 Transmit
UART2 Receive
Reserved
ISS_DMA_REQ1
ISS_DMA_REQ2
ISS_DMA_REQ3
ISS Event 1
ISS Event 2
ISS Event 3
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
165
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