DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources (continued)
Cortex-A8
INTERRUPT NUMBER
ACRONYM
SOURCE
40
41
42
43
44-47
48
49
50
51
52-61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
3PGSWRXTHR0
3PGSWRXINT0
3PGSWTXINT0
3PGSWMISC0
–
EMAC Switch RX Threshold
EMAC Switch Receive
EMAC Switch Transmit
EMAC Switch Miscellaneous
Reserved
PCIINT0
PCIINT1
PCIINT2
PCIINT3
–
PCIe
PCIe
PCIe
PCIe
Reserved
GPIOINT3A
GPIOINT3B
SDINT0
SPIINT0
-
GPIO3
GPIO3
MMC/SD0
SPI0
Reserved
TINT1
TIMER1
TINT2
TIMER2
TINT3
TIMER3
I2CINT0
I2CINT1
UARTINT0
UARTINT1
UARTINT2
RTCINT
RTCALARMINT
MBINT
I2C0
I2C1
UART0
UART1
UART2
RTC
RTC Alarm
Mailbox
–
Reserved
PLLINT
MCATXINT0
MCARXINT0
MCATXINT1
MCARXINT1
–
PLL Recalculation Interrupt
McASP0 Transmit
McASP0 Receive
McASP1 Transmit
McASP1 Receive
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
SMRFLX_HDVICP
–
SmartReflex HDVICP Domain
Reserved
TINT4
TIMER4
TINT5
TIMER5
TINT6
TIMER6
TINT7
TIMER7
GPIOINT0A
GPIOINT0B
GPIOINT1A
GPIO0
GPIO0
GPIO1
160
Power, Reset, Clocking, and Interrupts
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