DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
7.5 Interrupts
The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
The ARM Cortex-A8 and Media Controller are capable of servicing these interrupts. The following sections
list the device interrupt mapping and multiplexing schemes.
7.5.1 ARM Cortex-A8 Interrupts
The ARM Cortex-A8 Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the
System peripherals and generating either IRQs or FIQs to the Cortex-A8. The AINTC has the capability to
handle up to 128 requests, and the priority of the interrupt inputs are programmable. Table 7-26 lists the
interrupt sources for the AINTC.
For more details on ARM Cortex-A8 interrupt control, see the Interrupt Controller section of the Chip Level
Resources chapter in the device-specific Technical Reference Manual.
Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources
Cortex-A8
INTERRUPT NUMBER
ACRONYM
SOURCE
0
1
EMUINT
COMMTX
COMMRX
BENCH
Cortex-A8 Emulation
Cortex-A8 Emulation
Cortex-A8 Emulation
Cortex-A8 Emulation
ELM
2
3
4
ELM_IRQ
–
5
Reserved
6
–
Reserved
7
NMI
NMIn Pin
8
–
Reserved
9
L3DEBUG
L3APPINT
TINT8
L3 Interconnect
L3 Interconnect
TIMER8
10
11
12
13
14
15
16
17
18
19
20-27
28
29
30
31
32
33
34
35
36
37
38
39
EDMACOMPINT
EDMAMPERR
EDMAERRINT
WDTINT0
–
EDMA CC Completion
EDMA Memory Protection Error
EDMA CC Error
Watchdog Timer 0
Reserved
USBSSINT
USBINT0
USBINT1
–
USB Subsystem
USB0
USB1
Reserved
SDINT1
MMC/SD1
SDINT2
MMC/SD2
I2CINT2
I2CINT3
GPIOINT2A
GPIOINT2B
USBWAKEUP
PCIeWAKEUP
DSSINT
–
I2C2
I2C3
GPIO2 A
GPIO2 B
USB Subsystem Wakeup
PCIe Wakeup
HDVPSS
Reserved
HDMIINT
ISS_IRQ_5
HDMI
ISS
Copyright © 2013, Texas Instruments Incorporated
Power, Reset, Clocking, and Interrupts
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