DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 7-24. Maximum SYSCLK Clock Frequencies (continued)
MAX CLOCK FREQUENCY
OPP100 (MHz)
SYSCLK
SYSCLK18
SYSCLK19
SYSCLK20
SYSCLK21
SYSCLK22
SYSCLK23
0.032768
192
192
192
RSV
RSV
7.4.8 Module Clocks
Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM SYSCLK output. Table 7-25 lists the clock source options for each Module on this device, along
with the maximum frequency that Module can accept. To ensure proper Module functionality, the device
PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.
Table 7-25. Maximum Module Clock Frequencies
MAX FREQUENCY
OPP100 (MHz)
MODULE
CLOCK SOURCE(S)
PLL_ARM
SYSCLK18
Cortex-A8
600
DDR0
DMM
PLL_DDR
PLL_DDR/2
SYSCLK4
400
200
220
EDMA
SERDES
PLL_VIDEO0
EMAC Switch (GMII)
EMAC Switch (RGMII)
Fixed 125
Fixed 250
PLL_VIDEO0
SERDES
SERDES
PLL_VIDEO0
EMAC Switch (RMII and MII)
Fixed 50
EMAC_RMREFCLK Pin
Face Detect
GPIO
SYSCLK4
SYSCLK6
220
110
GPIO Debounce
GPMC
SYSCLK18
SYSCLK6
Fixed 0.032768
110
HDMI
PLL_VIDEO2
SYSCLK10
186
HDMI CEC
Fixed 48
SYSCLK20
SYSCLK21
AUD_CLK0/1/2
AUX Clock
HDMI I2S
50
HDVICP2
HDVPSS
SYSCLK3
266
200
PLL_HDVPSS
PLL_VIDEO2
HDMI PHY
HDVPSS VOUT1
186
PLL_VIDEO1
PLL_VIDEO2
HDVPSS VOUT0
165
HDVPSS SD VENC
PLL_VIDEO0
Fixed 54
PLL_VIDEO0
PLL_VIDEO1
HDMI
HDVPSS HD VENC
Fixed 148.5
I2C0/1/2/3
ISS
SYSCLK10
PLL_ MEDIACTL
SYSCLK4
48
400
220
L3 Fast
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Power, Reset, Clocking, and Interrupts
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