DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
8.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external
logic hardware such as buffers may be used to compensate any timing differences.
8.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
NOTE
For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
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