DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
www.ti.com
PLL_HDVPSS
PLL_MEDIACTL
HDVPSS
ISS, Media Controller
SYSCLK4
SYSCLK6
L3 Fast/Medium, L4 Fast,
EDMA, OCMC
PLL_L3L4
PRCM
L3/L4 Slow, GPMC,
ELM, McASP,
Mailbox, Spinlock
USB0/1
CLKDCO
PLL_USB
SYSCLK10
SYSCLK8
SPI0/1/2/3, I2C0/1/2/3,
UART0/1/2, HDMI CEC
DEVOSC/
DEV_CLKIN
M
U
X
CLKOUT
PRCM
MMC0/1/2
AUXOSC/
AUX_CLKIN
(Note: Separate MUX
exists for each PLL)
PLL_DDR
DDR
/2
DMM
HDVPSS SD VENC
PLL_VIDEO0
PLL_VIDEO2
HDMI
HDVPSS VOUT1
M
U
X
M
U
X
HDMI PHY
PLL_VIDEO1
PLL_AUDIO
HDVPSS HD VENC
HDVPSS VOUT0
M
U
X
SYSCLK20
SYSCLK21
PRCM
PRCM
M
U
X
MCASP0/1 AUX_CLK,
ATL
From PLL_VIDEO0/1/2
M
U
X
HDMI I2S
From AUX Clock, AUD_CLK0/1/2
PLL_ARM
(Embedded PLL)
M
U
X
Cortex-A8
RTCDIVIDER
SYSCLK18
RTC, GPIO, SyncTimer,
Cortex-A8 (Optional)
PRCM
From CLKIN32 Pin
M
U
X
TIMER1/2/3/4/5/6/7/8
From DEV/AUX Clock, AUD_CLK0/1/2, TCLKIN
WDT0 (Optional)
SmartReflex
M
U
X
SERDES
(Embedded PLL)
SERDES_CLK
M
U
EMAC Switch
From PLL_VIDEO0
X
PCIE SERDES
(Embedded PLL)
WDT0 (Optional)
RCOSC32K
Figure 7-7. System Clocking Overview
146
Power, Reset, Clocking, and Interrupts
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