DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
7.4 Clocking
The device clocks are generated from several reference clocks that are fed to on-chip PLLs and dividers
(both inside and outside of the PRCM Module). Figure 7-7 shows a high-level overview of the device
system clocking structure (Note: to reduce complexity, not all clocking connections are shown). For
detailed information on the device clocks, see the Clock Generation and Management section of the
Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical
Reference Manual.
NOTE
For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).
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Power, Reset, Clocking, and Interrupts
145
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