DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Power Supplies Stable
DEV_CLKIN/
AUX_CLKIN
POR
1
RESET
8
6
10
BTMODE[11](A)
Hi-Z
Hi-Z
RSTOUT_WD_OUT
4
4
5
2
3
BTMODE[15:0]
Other I/O Pins(B)
Config
5
RESET STATE
A. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.
B. For more detailed information on the RESET STATE of each pin, see Section 7.3.17, Pin Behaviors at Reset. Also
see , Terminal Functions for the IPU/IPD settings during reset.
Figure 7-6. Warm Reset (RESET) Timing
144
Power, Reset, Clocking, and Interrupts
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