CC1110Fx / CC1111Fx
12.8.6
Sleep Timer Registers
Note: All port interrupts are blocked when
SLEEP.MODE≠00
This section describes the SFRs associated
with the Sleep Timer.
12.8.5
Sleep Timer DMA Trigger
There is one DMA trigger associated with the
Sleep Timer. This is the DMA trigger ST,
which is generated when Event 0 occurs.
WORTIME0 (0xA5) - Sleep Timer Low Byte
Bit
Field Name
Reset
R/W
Description
7:0
WORTIME[7:0]
0x00
R
8 LSB of the16 bits selected from the 31-bit Sleep Timer according to the
setting of WORCTRL.WOR_RES[1:0]
WORTIME1 (0xA6) - Sleep Timer High Byte
Bit
Field Name
Reset
R/W
Description
7:0
WORTIME[15:8]
0x00
R
8 MSB of the16 bits selected from the 31-bit Sleep Timer according to the
setting of WORCTRL.WOR_RES[1:0]
WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High
Bit
Field Name
Reset
R/W
Description
7:0
EVENT0[15:8]
0x87
R/W
High byte of Event 0 timeout register
Sleep Timer clocked by low power
RCOSC
Sleep Timer clocked by 32.768 kHz
crystal oscillator
750
1
EVENT0 25WOR _ RES
tEvent0
EVENT0 25WOR _ RES
tEvent0
fref
32768
WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low
Bit
Field Name
Reset
R/W
Description
Low byte of Event 0 timeout register
7:0
EVENT0[7:0]
0x6B
R/W
SWRS033H
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