CC1110Fx / CC1111Fx
12.7 MAC Timer (Timer 2)
The MAC timer is designed for slot timing
operations used by the MAC layer in an RF
protocol. The timer includes a highly tunable
prescaler allowing the user to select a timer
interval that equals, or is an integer fraction of,
a transmission slot.
prescaler value, T2PR, defines the 8 MSB of
the 18 bit counter and thus set the maximum
value.
The timer 2 interval / time slot, T, can be given
as:
T = T2PR Val(T2CTL.TIP)/ timer tick speed,
8-bit timer
where the function Val(x) is set by T2CTL.TIP
and defined as
18-bit tunable prescaler
Val(00) = 64
Val(01) = 128
Val(10) = 256
Val(11) = 1024
Example:
12.7.1
Timer Operation
This section describes the operation of the
timer.
The timer count can be read from the T2CT
SFR. At each active clock edge, the timer
count is decremented by one. When the timer
count reaches 0x00, the register bit
T2CTL.TEX is set to 1. When T2CTL.TIG=0,
the timer will not wrap around when the timer
count reaches 0x00. When T2CTL.TIG=1,
timer count will wrap around and start counting
down from 0xFF.
T2PR= 0x09
T2CTL.TIP= 10
CLKCON.TICKSPD = 101 (812.5 kHz @ when
fxosc = 26 MHz)
T = 9 ∙ 256 / 812.5 kHz = 2.84 ∙10-3 s
If T2CTL.INT=1, IRCON.T2IF will also be
asserted when T2CTL.TEX is set to 1. An
interrupt request will be generated if both
T2CTL.INTand IEN1.T2IEare set to 1.
12.7.2
Timer 2 DMA Trigger
There is one DMA trigger associated with
Timer 2. This is the DMA trigger T2_OVFL,
which is generated when T2CTL.TEX is set to
1.
When a new value is written to the timer count
register, T2CT, this value is stored in the
counter immediately. If an active clock edge
and a write to T2CT occur at the same time,
the written value will be decremented before it
is stored.
12.7.3
Timer 2 Registers
The SFRs associated with Timer 2 are listed in
this section. These registers are the following:
The 18 bit prescaler is controlled by:
Timer tick speed (CLKCON.TICKSPD)
T2CTL.TIP
Prescaler value (T2PR)
T2CTL- Timer 2 Control
T2PR- Timer 2 Prescaler
T2CT- Timer 2 Count
All events in timer 2 are aligned to timer tick
Note: These registers will be in their reset
state when returning to active mode from
PM2 and PM3.
speed
given
by
CLKCON.TICKSPD.
T2CTL.TIP defines how fast the prescaler
counter counts up towards its maximum value
where it is reset and starts over again. The
SWRS033H
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