ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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8.6.15 CH1_CFG Register (Address = Eh) [reset = 0000h]
The CH1_CFG register is shown in 图8-40 and described in 表8-28.
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图8-40. CH1_CFG Register
15
14
13
12
11
10
9
1
8
0
PHASE1[9:2]
R/W-0000000000b
7
6
5
4
3
2
PHASE1[1:0]
R/W-0000000000b
RESERVED
R-000b
DCBLK1_DIS0
R/W-0b
MUX1[1:0]
R/W-00b
表8-28. CH1_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:6
PHASE1[9:0]
R/W
0000000000
b
Channel 1 phase delay
Phase delay in modulator clock cycles provided in two's complement
format. See 表8-5 for details.
5:3
2
RESERVED
R
000b
0b
Reserved
Always reads 000b
DCBLK1_DIS0
R/W
DC block filter for channel 1 disable
0b = Controlled by DCBLOCK[3:0] (default)
1b = Disabled for this channel
1:0
MUX1[1:0]
R/W
00b
Channel 1 input selection
00b = AIN1P and AIN1N (default)
01b = ADC inputs shorted
10b = Positive DC test signal
11b = Negative DC test signal
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