ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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8.6.13 CH0_GCAL_MSB Register (Address = Ch) [reset = 8000h]
The CH0_GCAL_MSB register is shown in 图8-38 and described in 表8-26.
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图8-38. CH0_GCAL_MSB Register
15
14
13
12
11
10
9
1
8
0
GCAL0_MSB[15:8]
R/W-10000000b
7
6
5
4
3
2
GCAL0_MSB[7:0]
R/W-00000000b
表8-26. CH0_GCAL_MSB Register Field Descriptions
Bit
15:0
Field
GCAL0_MSB[15:0]
Type
Reset
Description
R/W
1000000000
000000b
Channel 0 gain calibration register bits [23:8]
8.6.14 CH0_GCAL_LSB Register (Address = Dh) [reset = 0000h]
The CH0_GCAL_LSB register is shown in 图8-39 and described in 表8-27.
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图8-39. CH0_GCAL_LSB Register
15
14
13
12
11
10
2
9
1
8
0
GCAL0_LSB[7:0]
R/W-00000000b
7
6
5
4
3
RESERVED
R-00000000b
表8-27. CH0_GCAL_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
7:0
GCAL0_LSB[7:0]
RESERVED
R/W
00000000b
Channel 0 gain calibration register bits [7:0]
R
00000000b
Reserved
Always reads 00000000b
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