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ADS131B04-Q1 参数 Datasheet PDF下载

ADS131B04-Q1图片预览
型号: ADS131B04-Q1
PDF下载: 下载PDF文件 查看货源
内容描述: [汽车类 24 位 32kSPS 4 通道同步采样 Δ-Σ ADC]
分类和应用:
文件页数/大小: 77 页 / 2316 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ADS131B04-Q1  
ZHCSMK3B NOVEMBER 2020 REVISED NOVEMBER 2021  
www.ti.com.cn  
8.5.1.6 SPI Communication Frames  
SPI communication on the ADS131B04-Q1 is performed in frames. Each SPI communication frame consists of  
several words. The word size is configurable as either 16 bits, 24 bits, or 32 bits by programming the  
WLENGTH[1:0] bits in the MODE register.  
The interface is full duplex, meaning that the interface is capable of transmitting data on DOUT while  
simultaneously receiving data on DIN. The input frame that the host sends on DIN always begins with a  
command. The first word on the output frame that the device transmits on DOUT always begins with the  
response to the command that was written on the previous input frame. The number of words in a command  
depends on the command provided. For most commands, there are six words in a frame. On DIN, the host  
provides the command, the command CRC if input CRC is enabled or a word of zeros if input CRC is disabled,  
and four additional words of zeros. Simultaneously on DOUT, the device outputs the response from the previous  
frame command, four words of ADC data representing the four ADC channels, and a CRC word. 8-14 shows  
a typical command frame structure.  
DRDY  
CS  
SCLK  
DIN  
Command  
CRC  
Command  
CRC  
DOUT  
Hi-Z  
Response  
Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data  
CRC  
Hi-Z  
Response  
Channel 0 Data  
8-14. Typical Communication Frame  
There are some commands that require more or less than six words. In the case of a read register (RREG)  
command where more than a single register is read, the response to the command contains the  
acknowledgment of the command followed by the register contents requested, which may require a shorter or  
longer frame depending on how many registers are read. See the RREG command section for more details on  
the RREG command.  
In the case of a write register (WREG) command where more than a single register is written, the frame extends  
to accommodate the additional data. See the WREG command section for more details on the WREG  
command.  
See the Commands section for a list of all valid commands and their corresponding responses on the  
ADS131B04-Q1.  
Under special circumstances, a data frame can be shortened by the host. See the Short SPI Frames section for  
more information about artificially shortening communication frames.  
Copyright © 2022 Texas Instruments Incorporated  
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