DS_8430_001
78Q8430 Data Sheet
7.7.8 PHY Vendor Specific Register – MR16
Bits
15
Symbol
RSVD
RSVD
RSVD
TXHIM
Type Default Description
R
R
0
0
0
0
Reserved
14
Reserved
13
R
Reserved
12
R/W
Transmitter High-Impedance Mode
When set, the TXOP/TXON transmit pins and the TX_CLK pin
are put into a high-impedance state. The receive circuitry
remains fully functional.
11
10
SQEI
NL10
R/W
R/W
0
0
SQE Test Inhibit
Setting this bit to 1 disables 10Base-T SQE testing. By
default, this bit is 0 and generates a COL pulse following the
completion of a packet transmission to perform the SQE test.
10Base-T Natural Loopback
Setting this bit to 1 causes transmit data received on the
TXD0-3 pins to be automatically looped back to the RXD0-3
pins when 10Base-T mode is enabled.
9
8
7
6
5
RSVD
RSVD
RSVD
RSVD
APOL
R
R
0
1
0
1
0
Reserved
Reserved
Reserved
Reserved
R
R
R/W
Auto Polarity
During auto-negotiation and 10BASE-T mode, the 78Q8430
PHY is able to automatically invert the received signal due to a
wrong polarity connection. It does so by detecting the polarity
of the link pulses. Setting this bit to 1 disables this feature.
4
RVSPOL
R/W
0
Reverse Polarity
The reverse polarity is detected either through 8 inverted
10Base-T link pulses (NLP) or through one burst of inverted
clock pulses in the auto-negotiation link pulses (FLP). When
the reverse polarity is detected and if the Auto Polarity feature
is enabled, the 78Q8430 PHY will invert the receive data input
and set this bit to 1. If Auto Polarity is disabled, then this bit is
writeable. Writing a 1 to this bit forces the polarity of the
receive signal to be reversed.
3:2
1
RSVD
R/W
R/W
0h
0
Reserved. Must set to 00.
PCSBP
PCS Bypass Mode
When set, the 100Base-TX PCS and scrambling/
descrambling functions are bypassed. Scrambled 5-bit code
groups for transmission are applied to the TX_ER, TXD3-0
pins and received on the RX_ER, RXD3-0 pins. The RX_DV
and TX_EN signals are not valid in this mode. PCSBP mode
is valid only when 100Base-TX mode is enabled and auto-
negotiation is disabled.
0
RXCC
R/W
0
Receive Clock Control
This function is valid only in 100Base-TX mode. When set to
1, the RX_CLK signal will be held low when there is no data
being received (to save power). The RX_CLK signal will
restart 1 clock cycle before the assertion of RX_DV and will be
shut off 64 clock cycles after RX_DV goes low. RXCC is
disabled when loopback mode is enabled (MR0.14 is high).
This bit should be kept at logic zero when PCS Bypass mode
is used.
Rev. 1.2
79
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
