78Q8430 Data Sheet
DS_8430_001
7.7.9 PHY Interrupt Control / Status Register – MR17
The Interrupt Control/Status Register provides the means for controlling and observing the events that
trigger an interrupt on the internal PHY interrupt signal. This register can also be used in a polling mode
via the MII Serial Interface as a means to observe key events within the PHY via one register address.
Bits 0 through 7 are status bits, which are each set to logic one based upon an event. These bits are
cleared after the register is read. Bits 8 through 15 of this register, when set to logic one, enable their
corresponding bit in the lower byte to signal an interrupt on the PHY interrupt signal.
Bits
15
14
13
12
11
10
9
Symbol
Type Default Description
JABBER_IE
RXER_IE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RC
0
0
0
0
0
0
0
0
0
Jabber Interrupt Enable
Receive Error Interrupt Enable
PRX_IE
Page Received Interrupt Enable
Parallel Detect Fault Interrupt Enable
Link Partner Acknowledge Interrupt Enable
Link Status Change Interrupt Enable
Remote Fault Interrupt Enable
PDF_IE
LP_ACK_IE
LS_CHANGE_IE
RFAULT_IE
ANEG-COMP_IE
JAB_INT
8
Auto-Negotiation Complete Interrupt Enable
7
Jabber Interrupt
This bit is set high when a Jabber event is detected by
the 10Base-T circuitry.
6
5
4
3
2
1
0
RXER_INT
RC
RC
RC
RC
RC
RC
RC
0
0
0
0
0
0
0
Receive Error Interrupt
This bit is set high when the RX_ER signal transitions
high.
PRX_INT
Page Received Interrupt
This bit is set high when a new page has been
received from the link partner during auto-negotiation.
PDF_INT
Parallel Detect Fault Interrupt
This bit is set high by the auto-negotiation logic when a
parallel detect fault condition is indicated.
LP_ACK_INT
LS_CHANGE_INT
RFAULT_INT
ANEG_COMP_INT
Link Partner Acknowledge Interrupt
This bit is set high by the auto-negotiation logic when
FLP bursts are received with the acknowledge bit set.
Link Status Change Interrupt
This bit is set when the link status transitions from an
OK status to a FAIL status, or vice versa.
Remote Fault Interrupt
This bit is set when a remote fault condition is
detected.
Auto-Negotiation Complete Interrupt
This bit is set by the auto-negotiation logic upon
completion of auto-negotiation.
7.7.10 PHY Transceiver Control Register – MR19
Bit
Symbol
Type Default Description
15:14
TXO[1:0]
R/W
01
Transmit Amplitude Selection
Sets the transmit output amplitude to account for transmit
transformer insertion loss.
00 = Gain set for 0.0dB of insertion loss
01 = Gain set for 0.4dB of insertion loss
10 = Gain set for 0.8dB of insertion loss
11 = Gain set for 1.2dB of insertion loss
13:0
RSVD
R/W
XXX
Reserved
80
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
