DS_8430_001
78Q8430 Data Sheet
7.7.11 PHY Diagnostic Register – MR18
This register contains both user accessible and non-user accessible bits (Reserved) for internal
testmodes. The user-accessible bits are located at bit 12:8 locations.
Bit
Symbol
RSVD
Type Default Description
15:13
12
R
0
0
Reserved
ANEGF
RC
Auto-Negotiation Fail Indication
This bit is set when auto-negotiation completes and no
common technology was found. It remains set until read.
11
10
9
DPLX
RATE
RXSD
R
R
R
0
0
0
Duplex Indication
This bit indicates the result of the auto-negotiation for
duplex arbitration as follows:
0 = half duplex was the highest common denominator
1 = full duplex was the highest common denominator
Rate Indication
This bit indicates the result of the auto-negotiation for data
rate arbitration as follows:
0 = 10Base-T was the highest common denominator
1 = 100Base-TX was the highest common denominator
Receiver Signal Detect Indication
In 10Base-T mode, this bit indicates that Manchester data
has been detected. In 100Base-TX mode, it indicates that
the receive signal activity has been detected (but not
necessarily locked on to).
8
RXLCK
RSVD
R
R
0
0
Receive PLL Lock Indication
Indicates that the Receive PLL has locked onto the receive
signal for the selected speed of operation (10Base-T or
100Base-TX).
7:0
Reserved
7.7.12 PHY LED Configuration Register – MR23
Bit
Symbol
RSVD
Type
R/W
R
Default Description
Reserved
<1h> 0000 = Link OK
0001 = RX or TX Activity (Default LED1)
15:8
7:4
0
LED1[3:0]
0010 = TX Activity
0011 = RX Activity
0100 = Collision
0101 = 100 BASE-TX mode
0110 = 10 BASE-T mode
0111 = Full Duplex
1000 = Link OK/Blink=RX or TX Activity
<0h> 0000 = Link OK (Default LED0)
0001 = RX or TX Activity
0010 = TX Activity
3:0
LED0[3:0]
R
0011 = RX Activity
0100 = Collision
0101 = 100 BASE-TX mode
0110 = 10 BASE-T mode
0111 = Full Duplex
1000 = Link OK/Blink=RX or TX Activity
Rev. 1.2
81
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
