DS_8430_001
78Q8430 Data Sheet
7.6 CTL Registers
7.6.1 DMA Control and Status Register
Name: DMA
Reset Val: 0x0000_0000
Block: CTL
Address: 0x100
Bits
31:18
17
Type Default Description
X
0
0
Reserved
RW
Read Mode
Once this bit is set the host interface will be in DMA read mode until the
bit is cleared by a write to this register.
16
RW
0
Write Mode
Once this bit is set the host interface will be in DMA write mode until the
bit is cleared by a read to this register.
15:10
9:0
X
0
0
Reserved
RW
Address
The location of the register to direct DMA access to.
7.6.2 Receive Packet Status Register
Name: RPSR Reset Val: 0x0000_0000
Type Default Description
Block: CTL
Address: 0x104
Bits
31
RO
RO
RO
RO
0
0
0
0
Done
When not set the packet is still in the process of ingressing the QUE.
30
29
28
Length Error
The packet length was not correct.
Truncated
The packet was truncated and is incomplete.
Collision
The packet suffered a collision and is incomplete.
27
26
RO
RO
0
0
MII Error
Dangling Byte
The received packet length was not an integer number of bytes.
25
RO
RO
RO
RO
0
0
0
0
CRC
Ethernet CRC checksum error.
24
Checksum
IP Header checksum error.
23:16
15:0
Classification
The packet classification results.
Count
The total number of bytes currently in the QUE for this packet. When
the Done bit is set, this represents the actual packet size.
7.6.3 Transmit Packet Status Register
Name: TPSR
Reset Val: 0x0E00_0000
Block: CTL
Address: 0x108
Bits
Type
Default Description
31
RO
0
Done
When not set, the frame is still in transmission. When set, the content is
egressing the QUE.
30
29
RO
RO
0
0
Halted
The packet was halted.
Truncated
The packet was truncated and is incomplete.
Rev. 1.2
59
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
