73S1217F Data Sheet
DS_1217F_002
Miscellaneous Control Register 1 (MISCtl1): 0xFFF2 Å 0x10
Table 16: The MISCtl1 Register
MSB
LSB
ANAPEN USBPEN USBCON
–
–
FRPEN
FLSH66
–
Bit
Symbol
Function
MISCtl1.7
MISCtl1.6
–
–
Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is
passed through with no change. When FRPEN = 0 a one-shot circuit that
shortens the Flash Read signal is enabled to save power. The Flash Read
pulse will shorten to 40 or 66ns (approximate based on the setting of the
FLSH66 bit) in duration, regardless of the MPU clock rate. For MPU clock
frequencies greater than 10MHz, this bit should be set high.
MISCtl1.5
FRPEN
When high, creates a 66ns Flash read pulse, otherwise creates a 40ns read
pulse when FRPEN is set.
MISCtl1.4
MISCtl1.3
FLSH66
–
0 = Enable the analog functions that generate VREF and bias current
MISCtl1.2 ANAPEN* functions. Setting high will turn off the VPD regulator and VCO/PLL
functions.
MISCtl1.1
MISCtl1.0
USBPEN 0 = Enable the USB differential transceiver.
USBCON USB pull-up resistor connect enable.
*Note: The ANAPEN bit should never be set under normal circumstances. Power down control should
only be initiated via use of the PWRDN bit in MISCtl0.
32
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
