DS_1217F_002
73S1217F Data Sheet
Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the
PWRDN bit to the assertion of the PWRDN Signal (32 MPU clocks) Refer to the Power Down sequence diagram.
PWRDN Signal
MISCtl0 - PWRDN
Analog functions
(VCO, PLL,
reference and bias
circuits, etc.)
PD_ANALOG
+
MISCtl1 - ANAPEN
VDDFCtl - VDDFEN
MISCtl1 - USBPEN
VDDFAULT
+
+
+
USB
SUSPEND
USB Transceiver
(suspend mode)
ANALOG
COMPARE
ACOMP - CMPEN
MCLCKCtl - 32KEN
32K OSC
High Speed OSC
+
MCLCKCtl - HOSEN
Smart Card Power
+
+
SCVCCCtl - SCPRDN
MISCtl1 - FRPEN
Flash Read Pulse
one-shot circuit
These are the registers and
the names of the control bits.
These are the
block references.
Figure 6: Power-Down Control
When the PWRDN bit is set, the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the
program to set the STOP bit in the PCON register. This delay will enable the program to properly halt the
core before the analog circuits shut down (high speed oscillator, VCO/PLL, voltage reference and bias
circuitry, etc.). The PDMUX bit in SFR INT5Ctl should be set prior to setting the PWRDN bit in order to
configure the wake up interrupt logic. The power down mode is de-asserted by any of the interrupts
connected to external interrupts 0, 4 and 5 (external USR[0:7], smart card and Keypad). These interrupt
sources are OR’ed together and routed through delay logic into INT0 to provide this functionality. The
interrupt will turn on the power to all sections that were shut off and start the clock subsystem. After the
clock subsystem clocks start running, the MPUCLK begins to clock a 512 count delay counter. When the
counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 7 shows
the detailed logic for waking up the 73S1217F from a power down state using these specific interrupt
sources. Figure 8 shows the timing associated with the power down mode.
Rev. 1.2
29
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
