73S1217F Data Sheet
DS_1217F_002
acknowledge this request by setting the SCPWRDN bit in the Smart Card VCC Control/Status Register
(VccCtl) high after it has completed all shutdown activities. When SCPWRDN is set high, the circuit will
deactivate the smart card interface if required and turn off all analog functions and the VDD supply for the
logic and companion circuits. The default state upon application of power is the “OFF” state unless
power is supplied to the VBUS supply. Note that at any time, the firmware may assert SCPWRDN and the
73S1217F will go into the “OFF” state (when VBUS is not present). If the OFF switch function is not
desired and the application does not need to shut down power on VDD, the ON_OFF input can be
permanently grounded which will automatically turn on VDD when power is supplied on any of the VPC,
VBAT or VBUS power supply inputs.
If power is applied to both VBAT and VBUS, the circuit will automatically consume power from only the VBUS
source. The 73S1217F will be unconditionally “ON” when VBUS is applied. If the VBUS source is removed,
the 73S1217F will switchover to the VBAT input supply and remain in the “ON” state. The firmware
should assert SCPWRDN based on no activity or VBUS removal to reduce battery power consumption.
When operating from VBUS, and not calling for VCC, the step-up converter becomes a simple switch
connecting VBUS to VP in order to save power. This condition is appropriate for the USB “SUSPEND”
state. The USB “SUSPEND” state requires the power supply current to be less than 500uA. In order to
obtain and meet this low current limitation, the firmware must configure the 73S1217F into a power-down
condition using less than 20uA from VDD.
Note: When the ON_OFF switch function is not needed, i.e. when the 73S1217F must be in an always-
ON state when using another supply than VBUS (VPC or VBAT), some external discrete components are
needed.
1.7.4 Power Control Modes
The 73S1217F contains circuitry to disable portions of the device and place it into a lower power standby
mode or power down the 73S1217F into its “OFF” mode. The standby mode will stop the core, clock
subsystem and the peripherals connected to it. This is accomplished by either shutting off the power or
disabling the clock going to the block. The miscellaneous control registers MISCtl0, MISCtl1 and the
Master Clock Control register (MCLKCtl) provide control over the power modes. The PWRDN bit in
MISCtl0 will set up the 73S1217F for either standby or “OFF” modes. Depending on the state of the
ON/OFF circuitry and power applied to the VBUS input, the 73S1217F will go into either standby mode or
power “OFF” mode. If system power is provided by, VBUS or the ON/OFF circuitry is in the “ON” state,
the MPU core will placed into standby mode. If the VBUS input is not sourcing power and the ON/OFF
circuitry is in the “OFF” state, setting the PWRDN bit will shut down the converter and VP will turn off.
This in turn will turn off the VDD supply and the 73S1217F will be turned “OFF”. The power down modes
should only be initiated by setting the PWRDN bit in the MISCtl0 register and not by manipulating
individual control bits in various registers. Figure 6 shows how the PWRDN bit controls the various
functions that comprise power down state
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Rev. 1.2
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