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73S1217F-IMR/F 参数 Datasheet PDF下载

73S1217F-IMR/F图片预览
型号: 73S1217F-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 总线供电80515的系统级芯片, USB , ISO 7816 / EMV ,密码键盘和更多 [Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More]
分类和应用: 多功能外围设备微控制器和处理器时钟
文件页数/大小: 140 页 / 1066 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S1217F Data Sheet  
DS_1217F_002  
PDMUX  
(FF94h:bit7)  
USR0  
USR1  
USR[7:0] Control  
MPU  
INT0  
USR2  
USR3  
USR4  
USR5  
USR6  
USR7  
0
1
USRxINTSrc set to  
4(ext INT0 high)  
or  
6(ext INT0 low)  
INT4  
INT5  
CE  
TC  
9 BIT CNTR  
CLR  
RESETB  
PWRDN  
(FFF1h:bit7)  
D
Q
PWRDN_analog  
CLR  
TC  
CE  
RESETB  
5 BIT CNTR  
Notes:  
CLR  
1. The counters are clocked by the MPUCLK  
2. TC - Terminal count (high at overflow)  
3. CE - Count enable  
RESETB  
Figure 7: Detail of Power-Down Interrupt Logic  
text  
t0  
PWRDN BIT  
PWRDN SIG  
EXT. EVENT  
t1  
t4  
t6  
INT0 to MPU  
MPU STOP  
t7  
t2  
ANALOG Enable  
t3  
t5  
PLL CLOCKS  
t0: MPU sets PWRDN bit  
t1: 32 MPU clock cycles after t0, the PWRDN SIG is asserted, turning all analog functions OFF.  
t2: MPU executes STOP instruction, must be done prior to t1.  
t3: Analog functions go to OFF condition. No Vref, PLL/VCO, Ibias, etc.  
text: An external event (RTC, Keypad, Card event, USB) occurs.  
t4: PWRDN bit and PWRDN signal are cleared by external event.  
t5: High-speed oscillator/PLL/VCO operating.  
t6: After 512 MPU clock cycles, INT0 to MPU is asserted.  
t7: INT0 causes MPU to exit STOP condition.  
Figure 8: Power-Down Sequencing  
30  
Rev. 1.2  
 
 
 
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